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语音信号μ/A律压缩的DSP软件实现(英文文献+中期报告+源代码+流程图)

更新时间:2010-3-27:  来源:毕业论文

语音信号μ/A律压缩的DSP软件实现(英文文献+中期报告+源代码+流程图)
This article is taken from <TMS320C54x DSP Functional Overview>
1.4 Memory
The minimum memory address range for the ’54x devices is 192K words —composed of 64K words in program space, 64K words in data space, and64K words in I/O space. Selected devices also provide extended programmemory space of up to 8M words. The program memory space contains theinstructions to be executed as well as tables used in execution. The datamemory space stores data used by the instructions. The I/O memory spaceinterfaces to external memory-mapped peripherals and can also serve as extra data storage space.
The ’54x DSPs provide both on-chip RAM and ROM to improve system performance and integration.
Table 1–3 shows the on-chip memory options available on the ’54x family ofDevices.
Table 1–3. On-Chip Memory Options
 1.4.1 On-Chip ROM
The ’54x devices include on-chip maskable ROM that can be mapped into program memory or data memory depending on the device. On-chip ROM is mapped into program space by the microprocessor/microcontroller (MP/MC) mode control pin. On-chip ROM that can be mapped into data space iscontrolled by the DROM bit in the processor mode status register (PMST). Thisallows an instruction to use data stored in the ROM as an operand.
Customers can arrange to have the ROM of the ’54x programmed withcontents unique to any particular application.
1.4.2 Bootloader
A bootloader is available in the standard ’54x on-chip ROM. This bootloader can be used to transfer user code from an external source to anywhere in the program memory at power up automatically. If the MP/MC pin of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard ’54x devices provide different ways to download the code to accommodate various system requirements:
  Parallel from 8-bit or 16-bit-wide EPROM
  Parallel from I/O space in 8-bit or 16-bit mode
  Serial port boot in 8-bit or 16-bit mode through the standard serial port, the TDM serial port, the buffered serial port (BSP), or the multichannel buffered serial port (McBSP)
  Host port interface boot (standard HPI, HPI8, and HPI16)
  Warm boot (restart of an application without reloading the code)
The bootloader options on each ’54x device are determined by the peripheral mix available on that device. See Table 1–1 for information on the peripherals available on each device.
On select devices, in addition to the bootloader, the standard on-chip ROM also contains complex FFT algorithms, m-law/A-law expansion tables, and a sine look-up table.
1.4.3 On-Chip Dual-Access RAM (DARAM)
Dual-access RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory space. DARAM can be mapped into program/data memory space by setting the OVLY bit in the PMST register.
1.4.4 On-Chip Single-Access RAM (SARAM)
Each of the SARAM blocks is a single-access memory. This memory is intended primarily to store data values; however, it can be used to store program as well. SARAM can be mapped into program/data memory space by setting the OVLY bit in the PMST register.
1.4.5 On-Chip Two-Way Shared RAM
Select 54x devices with multiple CPU cores include two-way shared RAM blocks that allow simultaneous program space access from two CPU cores.
Each CPU can perform a single access with zero-states to any location in the two-way shared RAM during each clock cycle.
This shared RAM is most efficiently used when the two CPUs are executing identical programs. In this case, the amount of program memory required for the application is effectively reduced by 50% since both CPUs can execute from the same RAM.
1.4.6 On-Chip Memory Security
A security feature is included on 54x devices to prevent the on-chip memory contents from being extracted by a user. This feature is enabled during the manufacturing process and is only available to customers that order custom ROM programming. Consequently, memory security cannot be enabled/disabled by the user.
When the memory security feature is enabled, access to on-chip memory is protected in the following ways:
Emulation access: The security feature completely disables the scan-based emulation capability of the ’54x to prevent the use of a debugger utility. Note that this only affects emulation, and does not prevent the use of the JTAG boundary scan test capability.
HPI access: On select devices, HPI accesses are restricted when the security feature is enabled. These restrictions are described in Table 1–4.
CPU access: The security feature prohibits the DSP CPU from accessing the on-chip memory. There are two levels of security associated with CPU accesses.
ROM security option. This option is the least secure, because it only protects the on-chip ROM and does not protect the on-chip RAM. When the ROM security www.lwfree.cn option is enabled, any instruction fetched from external memory or on-chip RAM is prohibited from accessing on-chip ROM and reads invalid data (0FFFFh). Only instructions fetched from the on-chip ROM can be used to access the contents of
the ROM.
ROM/RAM security option. This option is the most secure, because it protects both the on-chip ROM and the on-chip RAM. When the ROM/RAM security option is enabled, any instruction fetched from external memory is prohibited from accessing on-chip ROM or RAM and reads invalid data (0FFFFh). Only instructions fetched from on-chip ROM or on-chip RAM can access the on-chip memory. The ROM/RAM security option also internally forces the device into microcomputer mode (MP/MC bit forced to zero), preventing the ROM from being disabled.
Table 1–4. On-Chip Memory Secruity HPI Access Restrictions
 1.4.7 Program Memory
The standard external program memory space on the ’54x devices addresses up to 64K 16-bit words. Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows:
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
1.4.7.1 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These 934

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