基于0.5um工艺的2X8微弱信号读出电路版图设计

Layout design of a 2*8 Readout Circuit with weak signal based on 0.5μm CMOS technology
Abstract: Integrated circuit has entered the era of deep sub-micron and SOC. As the bridge connecting design and manufacturing, layout's status is essential. In various types of integrated circuits, analog integrated circuits due to the dependence of device characteristics more, so its performance is more closely under the influence of layout factors. Integrated circuit design is to design the graphics of integrated circuit's each physical layer process. Readout circuit has the important significance both in modern photoelectron and micro sensors. On the basis of the correct understanding of readout circuit structure, characteristics and principle, using the Cadence to design layout of a 2*8 readout circuit with weak signal. It needs to pass DRC and LVS verification.

1  引言    1
2  课题要求及设计方案    2 源自六/维-论;文;网!加7位QQ324,9114 www.lwfree.cn
3  课题设计前期准备    4
3.1  相关简介    4
3.1.1  集成电路    4
3.1.2  集成电路的发明    4
3.1.3  集成电路的发展    5
3.1.4  集成电路的未来发展趋势    6
3.1.5  集成电路分类    6
3.1.6  微弱信号的定义及采集    8
3.1.7  MOS场效应晶体管    9
3.2  读出电路概述    10
3.2.1  读出电路单元的分类    10
3.2.2  读出电路设计    13
3.3  集成电路版图设计    14
3.3.1  版图设计的概述    14
3.3.2  版图设计规则    15
3.3.3  版图验证    19
3.3.4  叉指晶体管    19
4  课题设计内容    21
4.1  总设计流程    21
4.2  CMOS集成电路    22
4.2.1  CMOS集成电路的特点    22
4.2.2  CMOS数字电路    23
4.3  2*8微弱信号读出电路设计原理    30
4.3.1  总体电路    30
4.4  2*8微弱信号读出电路版图绘制    35
4.4.1  基本单元电路的版图绘制    35
4.4.2  整级电路的版图绘制    41
4.5  2*8微弱信号读出电路版图验证    41
4.5.1  运行Diva DRC    42
4.5.2  运行Diva LVS    44
5  结论    47

1    引言

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