## 基于FPGA的全同步数字频率计设计+仿真图

Design for all synchronous digital frequency meter based on FPGA
Abstract
The commonly used method of measuring frequency has a lot of, such as direct frequency measurement method (M),cycle measurement method (T), precision method (M/T),all synchronous frequency measurement method, etc.The design of the identical frequency measurement method for the first three's advantage is its precision is higher.Its frequency measuring principle is a signal changed in T seconds time repeat N times,Then according to the definition of the signal frequency frequency is N/T.
This thesis expounds the method of frequency measurement,Compares the advantages and disadvantages between them,I proposed my own design for full with pacing frequency.Because of the gate has delayed effect,At the time the clock signal and the measured signal synchronous start counting,through the phase synchronization to eliminate the error,through a series of steps to frequency after counting.At last,stop counting again to achieve synchronization. 源&自:六-维(论!文)网/www.lwfree.cn
According to the design method of synchronous frequency meter, this thesis using Verilog language module design and compilation.Make use of EDA top-down design process, simulation and debugging of each module in QuartusII.Finally, the whole system simulation to verify the success of the design.
There are 11 pictures and 20 references in this design.
Key words：Frequency meter  verilog HDL   All synchronous   simulation

Abstract.Ⅱ

1 绪论1
1.1课题研究背景.1
1.2频率计概述.1
1.3频率计发展现状.2
1.4频率计设计原理和方法.2
1.5QuartusII的软件介绍.3
2 基于FPGA的系统设计.4
2.1EDA技术.4
2.2FPGA简介.4
2.3查找表的原理和结构.5
2.4基于FPGA的设计方法5
2.5Verilog HDL语言6
3 全同步测量频率方法7
3.1常用的测量频率的方法.7
3.2全同步数字频率计的设计方法.10
4 FPGA功能模块设计13
4.1计数器模块.13
4.2锁存器模块.14
4.3选择电路.15
4.4控制电路.16
4.5显示电路.17
4.6频率计整体电路.18
5 下载验证20
5.1系统配置.20
6 结论22

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